The present invention relates to the fabrication of integrated circuits, and more particularly to reticles (masks) used during the fabrication of integrated circuits.
Integrated circuit (IC) design typically utilizes computer simulation tools to help create a circuit schematic, which typically includes individual devices that are coupled together to perform a certain function. To actually fabricate an IC that performs this function, the circuit schematic must be translated into a physical representation known as a layout using computer-aided design (CAD) tools. The layout translates the discrete circuit elements of the circuit schematic into shapes that are used to construct the individual physical components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, and metal interconnections.
CAD tools that generate the layout are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. These design rules are often determined by certain processing and design limitations defined by the particular IC fabrication process in which the layout is to be used, such as design rules defining the minimum space tolerance between devices or interconnect lines that prevent undesirable interaction between devices or lines. Design rule limitations are frequently referred to as critical dimensions. For example, a critical dimension of a circuit is commonly defined as the smallest width of a metal line or the smallest space between metal lines that can be supported by an IC fabrication process. Consequently, the critical dimension determines the overall size and density of the IC.
The layout is optically transferred onto a semiconductor substrate using a series of lithographic reticles (masks) and an exposure tool. Photolithography is a well-known process for transferring geometric shapes (mask pattern portions) present on each reticle onto the surface of a semiconductor substrate (e.g., a silicon wafer) using the exposure tool (e.g., an ultra-violet light source). In the field of IC lithographic processing, a photosensitive polymer film called photoresist is normally applied to the wafer and then allowed to dry. The exposure tool is utilized to expose the wafer with the proper geometrical mask patterns by transmitting UV light or radiation through the reticles. After exposure, the wafer is treated to develop the mask images transferred to the photosensitive material. These masking images are then used to create the device features of the circuit.
An important limiting characteristic of an exposure tool is its resolution value. The resolution value for an exposure tool is defined as the minimum mask pattern feature that the exposure tool can repeatedly expose onto the wafer. As the critical dimensions defined by IC fabrication processes grow ever smaller, the resolution values of features formed on the reticles used to fabricate ICs in accordance with the IC fabrication processes become correspondingly smaller.
While critical dimensions of IC features continue to shrink, the complexity and, hence, the overall size of many modern ICs continues to increase. These complex IC structures often require conductive (e.g., metal) lines for connecting various regions of the IC structure that are both long and narrow (i.e., having widths defined by the critical dimension of IC fabrication process utilized to produce the complex IC). To produce these long, narrow conductive lines, reticles are needed with correspondingly long and narrow mask lines.
FIG. 1 is an exploded perspective view showing a simplified conventional reticle 100 that is used during the optical transfer of long, narrow lines onto a semiconductor substrate (e.g., a wafer) 120. Reticle 100 includes an opaque masking material (e.g., chrome) that is deposited on a transparent (e.g., glass) plate 105 and etched to form a lithographic mask pattern 110. In the present example, mask pattern 110 includes a relatively long first mask line 111, a relatively long second mask line 113 that is perpendicular to first mask line 111 and has an end 113A that is separated from first mask line 111 by a gap 115. In addition, mask pattern 110 may include additional mask structures, such as mask line 117 and mask line 119, also shown in FIG. 1. Note however, that the present invention is particularly directed to reticles on which these additional mask structures are significantly separated from elongated mask lines 111 and 113 for reasons that will become apparent below. Note that the depicted lengths, widths, and thicknesses of lines 111, 113 and 117 in FIGS. 1 and 2 are modified for descriptive purposes.
As depicted in FIG. 1, during an integrated circuit fabrication process, ultra-violet (UV) light or radiation emitted from an exposure tool (not shown) is transmitted through reticle 100, thereby forming an image 122 of mask pattern 110 on semiconductor substrate 120. As indicated by the tapered dashed lines in FIG. 1, the lithographic process typically utilizes an optical reduction system such that image 122 is substantially smaller than (e.g., xc2xc) the size of lithographic mask pattern 110. Image 122 is then utilized, for example, to control an etching process during which metal lines are formed on semiconductor substrate 120.
FIG. 2 is a plan view showing a portion of reticle 100 in which some of the masking material has melted and formed a bridge 130 across gap 115 between first line 111 and end 113A of second line 113. The present inventors have determined that long, narrow mask lines collect static charges during masking procedures, and that the static charges on adjacent mask lines induce opposite polarities. In loose mask patterns (i.e., mask pattern containing relatively few or widely disbursed mask structures), these opposite polarity charges can become significant, particularly at xe2x80x9cTxe2x80x9d intersections where perpendicular mask lines are separated by relatively small gaps. For example, referring to FIG. 2, first line 111 and second line 113 extend in perpendicular directions, and form a xe2x80x9cTxe2x80x9d intersection where the two lines are separated by a minimum distance (i.e., gap 115). According to electrostatic theory, opposite polarity charges 130(+) and 130(xe2x88x92) collect in a region 111A of first mask line 111 and end region 113A of second mask line 113, which are located on opposite sides of gap 115, and produces a rapid electrostatic discharge when the line-of-force density and air break down voltage between the metal lines reaches a critical condition. The electrostatic discharge generates high temperatures that can damage the glass plate of the reticle between the two metal lines, and can melt the metal mask pattern material to form a bridge 135 linking first line 111 to second line 113. When subsequently used in masking procedures, light transmission through the reticle is reduced by bridge 135, thereby producing an incorrect image on the underlying semiconductor substrate (e.g., substrate 120; see FIG. 1).
What is needed is a reticle that is modified to prevent bridging of the masking material between adjacent elongated mask lines, thereby facilitating the development of fabrication processes for increasingly large IC patterns.
It is known to add small square shaped dummy mask portions to a reticle in order to distribute charge more evenly across the reticle. But the preferred location and distance from the mask line has not been known.
The present invention is directed to a reticle having two or more elongated mask lines that is modified to include a pattern of dummy mask portions that are arranged adjacent to and parallel to at least one of the elongated mask lines and located a critical distance away from the elongated mask lines. As mentioned above, mask material (e.g., chrome) is conductive, and elongated mask lines collect static charges during IC fabrication procedures. Further, opposite charges tend to concentrate at xe2x80x9cTxe2x80x9d intersections where perpendicular mask lines are separated by a relatively small gap, and produce bridging between the mask lines when these charges reach a critical state, resulting in electrostatic discharge (ESD) that generates high temperatures capable of locally melting the mask and its substrate materials. When close enough to the elongated mask lines, the dummy mask portions serve to balance (i.e., distribute) the charge over the length of the elongated lines, thereby reducing the concentration of opposite polarity charges at the xe2x80x9cTxe2x80x9d intersections, and reducing the possibility of ESD damage.
In accordance with a first aspect of the present invention, the plurality of dummy mask portions are located at a minimum distance from the elongated mask lines (i.e., equal to or shorter than the gap separating the two elongated lines at the xe2x80x9cTxe2x80x9d intersection). In one embodiment, each dummy mask portion is square and has sides that are equal to the critical feature dimension defined by the IC fabrication process, and is spaced from the elongated line segment by an offset distance that corresponds to the critical gap dimension defined by the IC fabrication process. In another embodiment, each dummy mask portion is a rectangular shaped mask line segment that is substantially shorter (smaller) than the elongated lines, and is aligned with and spaced from other mask line segments parallel to at least one of the elongated mask lines. Unlike the elongated mask lines, short dummy mask portions collect relatively small static charges that attract corresponding small amounts of the large static charge collected on the elongated mask line. By positioning dummy mask portions along a significant length of the mask lines and spacing the dummy mask portions a minimum distance from the mask lines, the larger static charges collected in the mask lines are balanced over a greater area, thereby limiting the voltage difference across gaps separating two adjacent mask lines.
In accordance with a second aspect of the present invention, the dummy mask portions may either be sub-resolution (i.e., smaller than the (critical) resolution value of the reticle), formed from transparent conductive material, or located on non-critical regions of the mask. Sub-resolution dummy mask portions don""t cause transfer of the dummy mask image onto the underlying semiconductor substrate because they have widths that are smaller than the minimum resolution value for an exposure tool utilizing the reticle. Similarly, dummy mask portions formed from transparent conductive material (e.g., indium-tin oxide (ITO) or molybdenum silicide (MoSi)) are not transferred onto the underlying semiconductor substrate Alternatively, dummy portions larger than the critical resolution value may be located over non-critical regions of the semiconductor substrate (i.e., regions that can be easily removed or corrected during later fabrication steps, or regions in which the formation of isolated metal portions does not affect the underlying IC circuitry).
In one embodiment, the dummy mask portions. are long enough and close enough to the elongated mask lines to cooperate with the elongated mask lines to form a capacitor. The capacitor draws charge toward the gap between the two plates, and prevents accumulation of charge at a single point such as the T intersection discussed above. A single dummy mask line can be patterned to cooperate with two or more elongated mask lines to form two or more capacitors, again preventing charge buildup at a single point.
In another embodiment, a mask line arrangement forming a T intersection is modified so that the end of the mask line close to another mask line is curved to form a portion parallel to the other mask line, another way to distribute charge.
The present invention will be more fully understood in view of the following description and drawings.